Many electronic systems utilize modular design techniques to subdivide a complex system into individual modules, such as integrated circuits (ICs), rather than developing and implementing the complex system in its entirety as a single module. For example, most radio frequency (RF) transceivers utilize separate modules for baseband signals and RF signals. For example, to transmit data, a baseband module (e.g., a baseband integrated circuit or BBIC) generates the digital data, and a RF module (e.g., a RF integrated circuit or RFIC) translates the digital data from the baseband module into an analog RF signal that is provided to an antenna. Similarly, to receive data, the RF module converts an incoming RF signal received at the antenna into a digital form suitable for subsequent demodulation and/or processing by the baseband module.
In most transceiver systems, the baseband module generates timing signals for controlling when the RF module initiates a time-sensitive action, for example, increasing (or ramping) the power output of the power amplifier. Because of the time-sensitive nature of the timing signals, the performance and/or reliability of the transceiver may be adversely affected if the timing signals are not received by the RF module with precise timing. Prior art transceiver systems utilize parallel communications (or alternatively, a parallel interface) between the baseband module and the RF module. In these systems, the baseband module includes one or more communication channels dedicated to a particular timing signal, and the RF module includes corresponding communication channels. For example, the ICs may each include a pin dedicated to a particular timing signal, and the respective pins may be directly connected (e.g., via a trace or wire), thereby ensuring that the timing signals are accurately and reliably received by the RF module.
Modern transceiver systems utilize serial communications (or alternatively, a serial interface) between the baseband module and the RF module. The previously used parallel communication channels are consolidated into a shared serial communication channel and the baseband and RF modules are modified to support serialized messages (e.g., packets or frames) which convey information previously communicated in parallel. A scheduling mechanism manages or controls the order in which messages (e.g., packets or frames) are transmitted from the baseband module over the serial interface. Often, the packets are scheduled in a first in first out (FIFO) ordering. Generally, to accommodate the time-sensitive nature of timing signals, the scheduling mechanism in the baseband module interrupts the message stream and inserts a message representative of a timing signal within the message stream to ensure that it is received by the RF module substantially in real-time (e.g., at a fixed amount of time after the timing signal occurs). To prevent collisions, many communication standards and/or protocols guarantee that timing signals will not occur simultaneously or very close together (e.g., less than the minimum amount of time required to transmit an individual timing message). For example, the Universal Mobile Telecommunications System (UMTS) standard requires an offset of 1025 chips between receive (RX) and transmit (TX) slots, resulting in a time difference of 1024 chips between individual timing signals.
Many next generation standards and/or protocols allow for two timing signals to be generated simultaneously or very close together. The prior art scheduling mechanism transmits the timing messages in the order that the timing signals were received, i.e., the first timing message followed by the second timing message. The receipt of the second timing message at the RF module is delayed by transmission of the first timing message, and as a result, the second timing message is not received by the RF module substantially in real-time (i.e., a fixed amount of time after the second timing signal occurs). This delay in receiving the second timing message (the timing error) impacts the performance and/or reliability of the transceiver system, and can affect compliance with various communications standards or other applicable regulations.